The present invention relates to a process for the use of a binary register with n bistable cells making it possible to determine the ratio of two frequencies and to an apparatus for performing this process.
The invention more particularly applies to the determination of the ratio of two frequencies of periodic or random signals, as in the case of nuclear incidents.
A binary register with n bistable cells used in the process according to the invention is known. Such a register is e.g. marketed under reference 74197 by Cordura Company, San Diego, Calif. This type of register generally functions either as a binary counter, or as a shift register.
A binary register with n bistable cells comprises n interconnected bistables. Each bistable B.sub.i, with i being an integer such that 1&lt;i&lt;n has two stable states, namely an activated state represented by bit 1 and a non-activated state represented by bit 0. The state of a bistable is dependent on the input signals applied thereto. Thus, when activated a bistable B.sub.i represents the number 2.sup.(i-1) in decimal notation. Any integer can be written in the form of a sum of integral powers of 2. The multiplicative coefficients of these powers of 2 represent by juxtaposition said integer in binary notation. The state of the different bistables of a binary register consequently represents the content of the register in binary notation. Thus, when the bistables B.sub.5 and B.sub.3 of a binary register with five bistables are activated, the other bistables being at state 0, the content of the register in binary notation is equal to 10100, i.e. in decimal notation to: EQU 1.times.2.sup.4 +0.times.2.sup.3 +1.times.2.sup.2 +0.times.2.sup.1 +0.times.2.sup.0 =20
Thus, when operating as a binary counter, an input signal S.sub.1 in the form of a pulse train is supplied to a counting input of a binary register with n bistables from the first bistable B.sub.1 forming the same. The register content is incremented by one unit for each pulse of the signal S.sub.1. Thus, when the input bistable B.sub.1 is at state 0, it is activated by a pulse of signal S.sub.1 and passes to state 1. Conversely, when the bistable B.sub.1 is at state 1, it passes to state 0 and increments the following bistable B.sub.2. Bistable B.sub.2 passes to state 1 if its preceding state was 0 or passes to state 0 if its preceding state was 1 by incrementing bistable B.sub.3 and so on.
Thus, it is possible to deduce from the state of n bistables, the content of the register, i.e. the number of pulses received at the input of the register in binary notation, the bistable B.sub.1 representing the lowest order bistable and bistable B.sub.n the highest order bistable.
A binary register with n bistable cells can obviously function as a subtract counter by decreasing the content of the register by one unit for each pulse of signal S.sub.1.
When operating as a shift register, an input signal S.sub.2 in the form of a pulse train is supplied to a shift input of the register with n bistables. This signal S.sub.2 is simultaneously applied to all the bistables. The content of the register is shifted by one bistable for each pulse of signal S.sub.2 from bistable B.sub.n to bistable B.sub.1 with the introduction of a state 0 into bistable B.sub.n, which amounts to the division by two of the register content. If, for each pulse of signal S.sub.2, the register content is shifted by one bistable from bistable B.sub.1 to bistable B.sub.n with the introduction of a state 0 into bistable B.sub.1, this amounts to multiplying the register content by two. The same can take place by working on the content of the register in complement of two and by introducing a state 1 in the place of a state 0.